Document Classification Systems in Heterogeneous Computing Environments

Datacenter workloads demand high throughput, low cost and power efficient solutions. In most data centers the operating costs dominates the infrastructure cost. The ever growing amounts of data and the critical need for higher throughput, more energy efficient document classification solutions motivated us to investigate alternatives to the traditional homogeneous CPU based implementations of document classification systems. Several heterogeneous systems were investigated in the past where CPUs were combined with GPUs and FPGAs as system accelerators. The increasing complexity of FPGAs made them an interesting device in the heterogeneous computing environments and on the other hand difficult to program using Hardware Description languages. We explore the trade-offs when using high level synthesis and low level synthesis when programming FPGAs. Using low level synthesis results in less hardware resource usage on FPGAs and also offers the higher throughput compared to using HLS tool. While using HLS tool different heterogeneous computing devices such as multicore CPU and GPU targeted. Through our implementation experience and empirical results for data centric applications, we conclude that we can achieve power efficient results for these set of applications by either using low level synthesis or high level synthesis for programming FPGAs

Exploring Digital Logic Design Using Ballistic Deflection Transistors Through Monte Carlo Simulations

We present exploratory studies of digital circuit design using the recently proposed ballistic deflection transistor (BDT) devices. We demonstrate a variety of possible logic functions through simple reconfiguration of two drain-connected BDTs. We further propose the creation of a three-BDT logic cell to yield differential versions of each logic function, improving overall flexibility of BDT circuit design. Each of the proposed gate configurations has been verified through extensive numerical calculations using an in-house Monte Carlo simulator. Simulation results show that the proposed gate arrangements are capable of achieving 400-GHz operating frequencies at room temperature. A compact fit-based analytical model to aid circuit design using BDTs is also introduced.ROOTHz (FP7-243845